1. Field of the Invention
The present invention relates to an operational amplifier and an integrating circuit, and more particularly to an operational amplifier including a phase compensation capacitance, and an integral action.
2. Description of Related Art
Hitherto, there have been widely known integrating circuits outputting a signal representing a result of integrating current or voltage values of an input signal. Such integrating circuits operate while repeating an integration period in which charges are accumulated in a capacitor element (charging) and a reset period in which charges are released from the capacitor element (discharging). As signals are amplified by the integrating circuit, input noise components are amplified together with input signal components. However, it is possible to reduce input noise components by narrowing a bandwidth of the integrating circuit. In order to narrower a bandwidth of the integrating circuit driven with a predetermined period, it is necessary to shorten the reset period and lengthen the integration period.
A reset operation of the integrating circuit using an operational amplifier varies depending on a slew rate. The slew rate means a rate of change of an output signal on the rising or falling edge thereof. For increasing the slew rate to shorten the reset period, it is necessary to increase current consumption of the operational amplifier or reduce a phase compensation capacitance of the operational amplifier. The phase compensation capacitance is traded off for a circuit stability of the operational amplifier. Hence, in general, current consumption is increased, and the reset period is shortened.
FIG. 8 is a schematic diagram of a conventional integrating circuit using an operational amplifier. As shown in FIG. 8, the integrating circuit includes an operational amplifier Op, an input current source Ic, a reset switch SW, and an integral capacitance Ci. The operational amplifier Op has a non-inverting input terminal (positive terminal) applied with a reference voltage V_bias and an inverting input terminal (negative terminal) supplied with an input current Iin from an input current source Ic. Further, an integral capacitance Ci and a reset switch SW are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier Op. The integral capacitance Ci is charged/discharged by use of the current Iin from the input current source Ic. The integral of a voltage changed through the charging/discharging is evaluated and output from the output terminal as an output voltage V_out.
FIG. 9 is a timing chart of the conventional integrating circuit using an operational amplifier, which shows an operation of the integrating circuit of FIG. 8. The operational amplifier Op is applied with a reference voltage V_bias at a predetermined voltage level, and an analog input current or digital input current Iin that varies between a high level (+I) and a low level (−I). The reset switch SW is set to be turned ON for a predetermined period, at predetermined intervals.
An OFF period of the reset switch SW is an integration period over which a voltage changed through the charging/discharging of the integral capacitance Ci is integrated. Further, an ON period of the reset switch SW is a reset period in which the integrated voltage is reset to a reference voltage V_bias. During the integration period, the reset switch SW is turned OFF, and charges are accumulated/released to/from the integral capacitance Ci due to the input current Iin. As a result, the output voltage V_out is changed from the reference voltage V bias to a higher level (+V) or lower level (−V). During the reset period, the reset switch is turned ON, and charges are accumulated/released to/from the integral capacitance Ci. As a result, the output voltage V_out is changed from a high or low level to the reference voltage V_bias.
FIG. 10 is a circuit diagram showing the detailed configuration of the conventional integrating circuit shown in the schematic diagram of FIG. 8. To describe correspondences between FIGS. 8 and 10, in FIG. 10, reference numeral 517 denotes an operational amplifier Op; 518, an integral capacitance Ci; 519a, a reset switch SW; and 521, an input current source Ic.
The operational amplifier 517 is composed of a bias circuit 514, an operational amplifier stage 515, and a source-grounded amplifier stage 516. Moreover, an operational amplifier 517 additionally includes a phase compensation resistor 505, and a phase compensation capacitance 506 for preventing oscillation. In order to carry out an integral operation with the operational amplifier 517, an input current source 521, an integral capacitance 518, and a reset switch 519a are added to the operational amplifier 517. As shown in FIG. 9, the input current source 521 outputs a forward or reverse current Iin. The reset switch 519a is turned ON/OFF by means of a transfer gate 519 and an inverter 520 at a timing of FIG. 9.
The bias circuit 514 supplies constant current to a P-type MOSFET 510 from a constant current source 513. A current mirror circuit of the P-type MOSFET 510, a P-type MOSFET 511, and a P-type MOSFET 512 supplies the current I1 to the operational amplifier stage 515, and supplies a current I4 to the source-grounded amplifier stage 516. The operational amplifier stage 515 has a non-inverting input node 502a (positive node) applied with the reference voltage V_bias, and an inverting input node 501a(negative node) supplied with an input current Iin. The operational amplifier stage 515 executes differential amplification by a differential pair of P-type MOSFETs 501 and 502, and a current mirror circuit of N-type MOSFETs 503 and 504. In the source-grounded amplifier stage 516, a drain current of the N-type MOSFET 507 is changed in accordance with a voltage of a node 509 as an output terminal of the operational amplifier stage 515, and an output voltage V_out is changed.
In the integration period of FIG. 9, if the input current Iin flows to the full from the input current source 521 in the forward direction, the input current Iin charges the integral capacitance 518. As a result, reference voltage V_bias<<input voltage V_in, so all of the current I1 flows through the P-type MOSFET 502. Accordingly, the current I1 flows from the P-type MOSFET 502 to the phase compensation capacitance 506, and charges of the phase compensation capacitance 506 are released. In contrast, if the input current Iin flows to the full in the reverse direction, charges of the integral capacitance 518 are released due to the input current Iin. As a result, reference voltage V_bias>>input voltage V_in, so all the current I1 flows through the P-type MOSFET 501. Accordingly, a current flows from the phase compensation capacitance 506 to the N-type MOSFET 504 to thereby charge the phase compensation capacitance 506. As a result of charging/discharging the phase compensation capacitance 506, the output voltage V_out is changed.
In the reset period of FIG. 9, the reset switch 519a is turned ON, the integral capacitance 518 is being charged, and the phase compensation capacitance 506 is being charged/discharged to reset the output voltage V_out to reference voltage V_bias. If the output voltage V_out is lower than the reference voltage V_bias just before the reset operation, a current flows from the phase compensation capacitance 506 to the N-type MOSFET 504 to thereby charge the phase compensation capacitance 506 through the reset operation as described above. As a result, the output voltage V_out is changed from the low level to the reference voltage V_bias. Further, if the output voltage V_out is higher than the reference voltage V_bias just before the reset operation, current flows from the P-type MOSFET 502 to the phase compensation capacitance 506 through the reset operation to thereby discharge the phase compensation capacitance 506 as described above. As a result, the output voltage V_out is changed from the high level to the reference voltage V_bias.
If the current Iin flows to the full in the integration period, and in the reset period, under the condition of I4≧I1, a change rate of the output voltage V_out (slew rate)=current I1/phase compensation capacitance 506. The slew rate is determined based on the phase compensation capacitance 506 and the current I1 of the operational amplifier stage 515 (I4≧I1).
Incidentally, Japanese Unexamined Patent Publication No. 9-331482 and Japanese Patent Translation Publication No. 2000-516075 disclose a conventional integrating circuit using an operational amplifier.
In general, in the integrating circuit, if the reset period may be shortened in a predetermined period, for example, in the case where the bandwidth is narrowed to reduce the input noise components. In this case, it is necessary to execute the reset operation with reliability within a short reset period, so the slew rate of the operational amplifier should be increased in accordance with the short reset period. As described above, the slew rate is determined based on a current value of the operational amplifier stage and the phase compensation capacitance. Therefore, in order to increase the slew rate, it is necessary to increase a current value of the operational amplifier stage or reduce the phase compensation capacitance value.
On the other hand, a large integral capacitance becomes a load for the operational amplifier. Thus, in order to ensure circuit stability, a large phase compensation capacitance value is necessary. This is because, if the phase compensation capacitance value is increased, a first pole frequency ωp1 is lowered, and a phase margin as an index of circuit stability can be ensured.
As discussed above, a large phase compensation capacitance is necessary for the circuit stability. However, if the phase compensation capacitance is increased, the slew rate is lowered. Hence, in order to increase the slew rate, it is necessary to increase a current value of a differential input stage, resulting in a problem in that current consumption of the operational amplifier increases.